Even EDA Tool Users Can Save More Power
When EDA tools run out of steam, power optimizers can step up to the architectural level using ICE-G1. By considering application and IP core activity at the architectural level, Sonics’ ICE-G1 exploits idle moments not visible to software drivers and poorly served by EDA tools that perform automatic clock gating.
- Autonomous, hardware-based EPU identifies, sequences, and controls power state transitions up to 500X faster than conventional CPU-based approaches; EPUs exploit microsecond-level idle moments.
- Distributed power grain controllers enable parallel operation and deliver deterministic responsiveness to guarantee real-time deadlines.
- Coarse clock gating at a higher level than EDA-driven sequential clock gating eliminates dynamic power associated with all of the clocks connected to a power grain including clock distribution power.
- Retention voltage switching reduces the supply for a grain to a level where memory and/or flip-flop state is preserved, but logic operations are unsafe; this saves substantial leakage current without requiring identification of retention registers.
- Power gating disconnects the local supply for a grain from the global supply, completely eliminating the leakage current, while enabling rapid state recovery.
- Aggregation of savings techniques, abstraction of power control, and automation of EPU RTL and UPF generation enable scaling to finer grained power partitioning, while accelerating schedules.