An industry survey some three years ago indicated only about one-quarter of all chip designers were using dynamic voltage and frequency scaling (DVFS). It’s likely most of those people who said they were implementing DVFS are deeply dependent upon a mobile operating system. For instance, Android offers a range of CPU governor software modules to optimize frequency and voltage levels for application throughput. While DVFS is already enabled in most hardened CPU and GPU cores, clusters and/or subsystems, the majority of SoC designers not tied to Android opt for simpler techniques like clock and power gating. Is there an opportunity for a more holistic DVFS approach that more SoC designers would embrace?
Software sort of in control
The problem many teams cite with the current state of DVFS technology is that improving battery life requires optimizing for energy use, while most software-based control approaches instead minimize power dissipation based on recent activity. How could one expect software to minimize energy, when it can predict neither the throughput requirements nor the energy trade-offs between the different power savings techniques? Add on the implications of process corners and temperature variation, and the energy cost just to run a more sophisticated prediction model in software, and designers start to look for easier solutions.
Case in point: a team at Georgia Tech studying the current Android DVFS solution published their findings earlier this year. In short, they highlight the existing stock Android governor framework is too general purpose, focused on power reduction rather than delivering overall energy savings. Worse still, multiple software governors “work independently of each other,” leading to performance and energy losses as they undo each other’s optimizations. *
The Georgia Tech team proposes a solution implementing coordinated control of CPU frequencies and memory bandwidth against a set of six applications executing on a Google Nexus 6 smartphone running Android Marshmallow 6.0. Their software-coordinated controller delivers a 4% to 31% energy savings across these use cases with less than a 1% performance loss in all cases. It’s on a highly simplified set of mobile energy use cases, but their study points to the potential for a better DVFS solution – one implemented by the SoC designer who has the best knowledge of the power versus throughput characteristics of each power savings technique.
A new idea: holistic DVFS
Complexity is the enemy of strictly software-based DVFS approaches. The more complex a mobile energy use case becomes, and the more components need power control, the harder it is for a software team to figure out all the necessary SoC IP sequencing to save energy without impacting performance. Hardware teams implement things like various levels of sleep modes that gate IP blocks between tasks, trying to keep it simple. However, we have reached the limits of energy savings achievable from “sleep harder” methods, especially with relatively slow software pushing the wake buttons.
Thinking of techniques like DVFS as independent from clock and power gating, body-biasing, and other power savings techniques is dead. Yet, the idea of integrating DVFS with these other techniques into a hardware-driven control system is very much alive. This holistic DVFS approach would expand control beyond the CPU and memory controller to enable a bigger impact with other IP subsystems – DSP, GPU, wireless baseband, video, audio, and others – fully managed in hardware.
By mapping the use case requirements onto the IP subsystems, the designer selects SoC-level operating points that define per-subsystem power states, and the transition conditions between them. Hardware controllers then manage the power state transitions, reacting to incoming events by sequencing clock and power gating, and varying frequencies and voltage with process and temperature compensation. Such an approach directly optimizes both performance and energy consumption.
Overlaying system-level energy management strategies with the capability of hardware-based control, able to autonomously execute sequences SoC-wide with faster, fine-grained resolution, makes holistic DVFS attractive. Fortunately for SoC designers, the R&D on such a hardware-based DVFS framework is already done.
EPU IP extends energy savings
Sonics has been showing how their Energy Processing Unit (EPU) IP enables designers to snatch back idle moments for energy savings, using hardware IP up to 500x faster than software approaches. Now, the EPU concept is extending to holistic DVFS with the release of Sonics ICE-P3 EPU IP, including body bias control for process technologies like Global Foundries 22FDX.
ICE-P3 builds on the features of ICE-G3, using the same EPU Studio development tools and correct-by-construction IP. ICE-G3 introduced the ideas of clusters defining coordinated power states and transitions for anywhere from one to many power grains. ICE-P3 extends the cluster states into full operating points defining up to four independent performance targets, each mapped to temperature-compensated values for up to four voltage and/or frequency sources. Arbitration in ICE-P3 allows different clusters to share the same voltage and frequency resources, supporting coordinated control. ICE-P3 also has resource controllers for PLLs, clock generators, voltage regulators, or PMIC interfaces to turn the transition requests into control signaling.
This autonomous, hardware-based control scheme reduces dynamic switching and static power leakage, major components of SoC power consumption at lower operating voltages. A step further in energy savings is possible using the option of FD-SOI body-biasing techniques under control of ICE-P3. Instead of only adjusting supply voltage and frequency, forward or reverse body bias can be applied to optimize transistor performance to match the energy use case of interest. Forward body bias (FBB) enhances switching performance, while reverse body bias (RBB) minimizes leakage.
In a May 2016 blog on the 22FDX Platform, I speculated about the possibility of using dynamic body bias under software control to slide the same implementation up and down the power-frequency curve. I stopped short of calling that DVFS at the time, but with the rollout of Sonics ICE-P3 and its hardware sequencing, using dynamic 22FDX body-biasing now makes total sense in a faster, more capable holistic DVFS approach.
Differentiation, openness, and IoT use cases
Three takeaways strike me around the idea of SoC designers using Sonics ICE-P3 for holistic DVFS:
- Differentiation on energy savings wins. Folks who avoided traditional DVFS, or are mired in gigantic spreadsheets trying to figure out sequences, now have IP automation on their side. SoC designers don’t have to give up any of their favorite hardware techniques to add holistic DVFS.
- Open source can ride back into the DVFS picture. Imagine what happens if the Android community devises a new and improved software governor framework leveraging holistic DVFS at hardware speeds – and it proves to work for more complex mobile energy use cases.
- IoT use cases need aggressive energy management. SoCs and MCUs designed for IoT edge and fog applications can match up use cases to holistic DVFS implementations for big energy savings.
Want to see how Sonics’ ICE-P3 and EPU Studio work? Hit the “Free Trial” button in the upper right.
* “Application-Specific Performance-Aware Energy Optimization on Android Mobile Devices”, Rao et al, Georgia Tech, 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA), February 2017.