IP Is EDA

Earlier this month I had the distinct pleasure of attending the EDA Consortium’s (EDAC) prestigious Phil Kaufman award dinner. This year’s winner is Lucio Lanza, managing director of Lanza techVentures, LLC. Lucio is an EDA industry legend. We used to bump into each other often in the Cadence hallways after both of our companies had been acquired by Cadence around 1989. I truly appreciated Lucio’s leadership style with the Artisan board of directors when I was Vice President of Corporate Ventures there. Lucio’s strategic insights and steady pressure to keep us focused on the critical items were a major factor in Artisan’s success.

In Cadence’s Richard Goering interview with Lucio about receiving the Kaufman award, he stated, IP is EDA, and IP is exactly the way EDA has been growing. Sonics could not agree more.

Sonics believes EDA and IP go hand-in-hand to help solve critical performance, complexity, ease of integration, and time-to-market issues for SoC designers. We engineer our on-chip network IP to be highly configurable to support a broad range of design types and market requirements. We marry our IP with GUI-driven configuration tools to make it easy for SoC designers of all abilities to work with our products. And, we partner with EDA tool vendors to ensure that our IP integrates seamlessly into their design flows and complies with industry standards that define IP exchange formats, open interface protocols, and established logical and physical design methods.

If you haven’t yet embraced a commercial IP strategy for on-chip networks in your SoC designs, perhaps it’s time to consider doing so.

Register now to attend our NoC 101 webinar on November 20th at 10:00am PT and learn more about the value of Sonics’ on-chip network IP for improving your SoC designs.

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