One often overlooked network on a chip is the power supply network. While not as glamorous as the communication network, it still provides an essential function and therefore, requires careful design and analysis.
The EDA companies have invested in the development of tools to perform design and analysis of many of the aspects of the power supply network to make sure we get it right. These aspects include the following.
- Power rail analysis – the size and connections between metal layers are analyzed to determine if the current carrying capability is sufficient for the given load. Too large of an IR drop in the supply network can affect the interface levels or reduce the performance of the circuit.
- Decoupling capacitance analysis – the size and location of on chip decoupling capacitance are analyzed to minimize local supply noise, but too much capacitance increases leakage.
- EM analysis – the size and connections between metal layers are analyzed to determine if there are any reliability issues related to metal failure.
- EMI analysis – the size and placement of power rails with respect to fast switching signals such as a clock can prevent electromagnetic interference.
One of the most popular on chip power management techniques used today to reduce power is that of power shut off. By switching the supply to zero, both the active and leakage portions of the power consumption are reduced to near zero. This gives us the maximum power saving for this portion of the chip with what looks to be some relatively simple control logic. But there is a hidden trap with power shut off. When re-energizing the logic, inrush currents can cause a significant supply problem. Since we must assume that leakage currents have probably discharged the internal nodes of the circuit, including any decoupling capacitance on the switched supply, many of those nodes must be re-charged as the local supply rails recover. The associated capacitance, and thus the total required charge, is much higher than associated with normal circuit operation, so the peak inrush current must be considered in power switch design.
Inrush currents do not negatively affect the logic being powered up, but instead impact other logic domains which are sharing the same supply. The large instantaneous changes in current caused by re-enabling power to shut off switches can be seen as sags on nearby supply or ground rails. These sags slow down circuits and can lead to operational failure. This is why EDA companies have added two additional capabilities to their power network analysis tools.
- Power switch sizing analysis – undersized switches can prevent normal operation of a logic domain, but too large of a switch can produce large inrush currents and can cause sags.
- Power switch sequencing analysis – switching too fast can cause sags in the supply or ground networks of neighboring domains, while switching too slowly wastes valuable domain active time.
These analysis tools, when combined with the previous set, give us a complete solution to analyze power shut off. All we need now is the proper control for power shut off. Sonics’ Energy Processing Units (EPUs) provide a highly configurable, hardware-based solution to power control.
Check back next week for part 2 of my blog that will look at the different types of power shut off control and how this applies to taming the inrush current.