Recently I attended a presentation at the Machine Learning Developers Conference held at the Santa Clara Convention Center. The presentation, “Overcoming the Memory System Challenge in Dataflow Processing”, was given jointly by Darren Jones of Wave Computing and Drew Wingard of Sonics. The presentation was indeed fascinating as Jones first described how dataflow processors are ideal for deep learning, especially as compared to using existing CPU and GPU architectures. Jones then showed some performance numbers for machine learning training using the Wave Computing solution. And that is when I had to scratch my head. I did not hear any gasps. Everyone just accepted this phenomenal piece of engineering – just took it in stride. “Are Incredible Engineering Feats Treated As Commonplace Today?”
Complexity and flexibility are the real drivers of fabric choice, not the number of initiators and targets. Since I first helped introduce the concept of applying networking techniques to address SoC integration challenges in 2007, I have been asked many hundreds of times how to determine when and where to best use an on-chip network (NoC) instead of a passive interconnect network (PIN)? Is there a minimum number of initiators and targets below which it makes more sense to use a PIN for the SoC architecture in “smaller” designs? “NoC Versus PIN: Size Matters”
Why a methodology for developing software is now required in hardware. History repeats itself, but frequently not in the exactly the same place. The problems faced by system engineering teams today rising complexity, shorter market windows and more issues involving interactions that affect everything from dynamic power and leakage current to electromigration and finFET design mirror the kinds of top-down issues that software developers began encountering more than two decades ago. “Get Agile”
There are four primary failure modes associated with NoCs. Recently, the reliability features of on-chip network (NoC) IP have received much attention. One reason for this focus has been the rush of companies to get into the automotive electronics market and the explosion of new automotive features being implemented in electronic systems. While the details may vary, the high-level view of on-chip network reliability is really quite simple. “NoC Reliability: Simplified”
Accellera Systems Initiative has released the tutorial “OCP: The Journey Continues” from the 2014 Design and Verification Conference. Now available online, the five-part tutorial presents the past, present and future of the Open Core Protocol IP interface socket standard, which was transferred to Accellera in 2013. The tutorial provides a basic introduction and then discusses a variety of topics crucial to the use of OCP in SoC designs: verification IP support, TLM 2.0 SystemC support and IP-XACT support. Presenters include Herve Alexanian of Sonics, Steve McMaster of Synopsys, Prashant Karandikar of Texas Instruments and me.
IP integration is central to Sonics’ on-chip network business and technology strategies. We founded our company in 1996 based on the promise of IP integration to address the increasing silicon real estate afforded by Moore’s Law. Our company name, Sonics, is an acronym for Systems On ICs. For nearly two decades, Sonics has been a champion for IP integration technologies and methodologies that serve the performance and productivity needs of SoC designers. We’ve partnered with the industry’s top semiconductor and systems companies to turn the promise of IP integration into SoC reality.
So what have we learned about the importance and effectiveness of IP integration during our journey?