Inrush Currents Tamed – Part 3

In part 1 and part 2 of my blog, we looked at the capabilities that the EDA tools provided in the area of supply network analysis as well as the different methods of power shut off control. In this third blog, we will look at inter-domain switch control and role it plays in further taming the inrush currents.

Inter-Domain Switching Control

We must also consider the inter-domain switching control methods during our supply network analysis. Here each method provides a way to control the simultaneous switching of multiple logic domains. Continue reading “Inrush Currents Tamed – Part 3”

Inrush Currents Tamed – Part 2

In part 1 of my blog, we looked at the capabilities that the EDA tools provide in the area of supply network analysis. Now, we look at the different methods of power shut off control in the supply network.

Power Shut Off Control

The various methods used to control power shutoff switches each provide a way to control inrush currents and a way to indicate when a stable supply level has been achieved. Generally speaking, they approach the problem of minimizing peak inrush current by starting with a large power switch resistance (since I = V/R) and then gradually reduce the effective resistance as the difference in voltage across the power switch decreases. Continue reading “Inrush Currents Tamed – Part 2”

Inrush Currents Tamed – Part 1

One often overlooked network on a chip is the power supply network. While not as glamorous as the communication network, it still provides an essential function and therefore, requires careful design and analysis.

The EDA companies have invested in the development of tools to perform design and analysis of many of the aspects of the power supply network to make sure we get it right. These aspects include the following.

  • Power rail analysis – the size and connections between metal layers are analyzed to determine if the current carrying capability is sufficient for the given load. Too large of an IR drop in the supply network can affect the interface levels or reduce the performance of the circuit.
  • Decoupling capacitance analysis – the size and location of on chip decoupling capacitance are analyzed to minimize local supply noise, but too much capacitance increases leakage.
  • EM analysis – the size and connections between metal layers are analyzed to determine if there are any reliability issues related to metal failure.
  • EMI analysis – the size and placement of power rails with respect to fast switching signals such as a clock can prevent electromagnetic interference.

Continue reading “Inrush Currents Tamed – Part 1”

UPF Versioning Nightmare Solved

Unified Power Format (UPF) has been an ever evolving standard started as a technical committee by the Accellera organization in 2006, producing the first revision of the UPF specification, UPF 1.0 in 2007. Soon after UPF 1.0 release the group reformed under the IEEE organization as IEEE1801 with a major goal of merging in a competing standard, the Common Power Format (CPF). IEEE 1801 has since released three new versions of the UPF specification over the past ten years: IEEE1801-2009 (UPF 2.0), IEEE1801-2013 (UPF 2.1) and IEEE1801-2015 (UPF 3.0).

UPF solves some unique problems in the design world. One is the lack of any need to consider power supplies in traditional digital design at the RTL level (or higher). Others cope with the desire to separate what is supported by an IP component from what is actually implemented on a given chip. From an IP developer’s view: How can I provide one functional description and let my user choose what power features to use and how to implement them? From a chip architect’s view: How can I describe the power structure on a chip without having to embed the architecture into every block of the functional description? Continue reading “UPF Versioning Nightmare Solved”

Saving Power with Temperature Compensation

There have been many blogs and articles written on power management utilizing dynamic voltage and frequency scaling (DVFS), a method by which a discrete voltage and frequency pair is chosen from a predetermined list based on an input requirement. For an example, read Don Dingee’s blog entitled “DVFS is Dead, Long Live Holistic DVFS.” Choosing this input requirement is where it all starts. Continue reading “Saving Power with Temperature Compensation”

DVFS is Dead, Long Live Holistic DVFS

An industry survey some three years ago indicated only about one-quarter of all chip designers were using dynamic voltage and frequency scaling (DVFS). It’s likely most of those people who said they were implementing DVFS are deeply dependent upon a mobile operating system. For instance, Android offers a range of CPU governor software modules to optimize frequency and voltage levels for application throughput. While DVFS is already enabled in most hardened CPU and GPU cores, clusters and/or subsystems, the majority of SoC designers not tied to Android opt for simpler techniques like clock and power gating. Is there an opportunity for a more holistic DVFS approach that more SoC designers would embrace? Continue reading “DVFS is Dead, Long Live Holistic DVFS”

Is Designing Your Chip Architecture Like Driving a Car with No Pedals?

For those of you that have been reading my blogs or watching my presentations for a while, you will know I like to use cars for analogies. They represent a system that everyone understands at a user level, they are composed of many subsystems, the details of which can get pretty complicated if you dig deep. So today, you will see how most chip architectures are designed like having a car without a gas pedal – and what you can do about it. Continue reading “Is Designing Your Chip Architecture Like Driving a Car with No Pedals?”

Taking Energy Back from Next-Generation MCU Designs

Microamp-per-megahertz thinking served the microcontroller (MCU) community well for decades. As the focus shifts to connectivity and always-on use cases, bigger cores and wireless IP blocks push energy use in the wrong direction. Next-generation MCUs can ill afford to spend more energy just to manage themselves. Any mandatory software to make an MCU run usually frustrates customers considering design-ins. How does the MCU ecosystem manage energy moving forward? Continue reading “Taking Energy Back from Next-Generation MCU Designs”

Best Practices for Power Management in SoCs Today

Interview with a Power Management Architect

Dynamic Power Management has become a ‘must-have’ in Systems-on-a-Chip (SoC) design today because of tightening power budgets and rising transistor counts. These increases mainly stem from evolving market requirements for more device functionality and richer feature sets being made available to meet changing market requirements. The semiconductor industry has responded with a plethora of different solutions to these issues.

Semico Research Corp. conducted an interview with Jawad Haj-Yihia, a Power Management Architect formerly of Intel Corp. in Israel. The following article represents key aspects of that interview delving into many of the issues that confront Power Management Architects in the industry today. Continue reading “Best Practices for Power Management in SoCs Today”

Free Trial Explores EPU IP and Automation

Last summer at 53DAC in Austin, Sonics rolled out a seminar with a formative strategy for its Energy Processing Unit, or EPU. After that session, I summarized the idea in my SemiWiki blog:

“The premise of an EPU is that power savings using software, even in a dedicated microcontroller, is relatively slow, perhaps 50 to 500 times slower than what hardware-based power control can handle. Faster speeds mean narrower moments of idle time can be exploited to save energy, and distributed, autonomous, deadlock-free ICE-Grain controllers mean many more of those moments can be processed all over the system-on-chip (SoC) – leaving the CPU to do real work.” Continue reading “Free Trial Explores EPU IP and Automation”