Inrush Currents Tamed – Part 3

In part 1 and part 2 of my blog, we looked at the capabilities that the EDA tools provided in the area of supply network analysis as well as the different methods of power shut off control. In this third blog, we will look at inter-domain switch control and role it plays in further taming the inrush currents.

Inter-Domain Switching Control

We must also consider the inter-domain switching control methods during our supply network analysis. Here each method provides a way to control the simultaneous switching of multiple logic domains. Continue reading “Inrush Currents Tamed – Part 3”

Inrush Currents Tamed – Part 2

In part 1 of my blog, we looked at the capabilities that the EDA tools provide in the area of supply network analysis. Now, we look at the different methods of power shut off control in the supply network.

Power Shut Off Control

The various methods used to control power shutoff switches each provide a way to control inrush currents and a way to indicate when a stable supply level has been achieved. Generally speaking, they approach the problem of minimizing peak inrush current by starting with a large power switch resistance (since I = V/R) and then gradually reduce the effective resistance as the difference in voltage across the power switch decreases. Continue reading “Inrush Currents Tamed – Part 2”

Inrush Currents Tamed – Part 1

One often overlooked network on a chip is the power supply network. While not as glamorous as the communication network, it still provides an essential function and therefore, requires careful design and analysis.

The EDA companies have invested in the development of tools to perform design and analysis of many of the aspects of the power supply network to make sure we get it right. These aspects include the following.

  • Power rail analysis – the size and connections between metal layers are analyzed to determine if the current carrying capability is sufficient for the given load. Too large of an IR drop in the supply network can affect the interface levels or reduce the performance of the circuit.
  • Decoupling capacitance analysis – the size and location of on chip decoupling capacitance are analyzed to minimize local supply noise, but too much capacitance increases leakage.
  • EM analysis – the size and connections between metal layers are analyzed to determine if there are any reliability issues related to metal failure.
  • EMI analysis – the size and placement of power rails with respect to fast switching signals such as a clock can prevent electromagnetic interference.

Continue reading “Inrush Currents Tamed – Part 1”

UPF Versioning Nightmare Solved

Unified Power Format (UPF) has been an ever evolving standard started as a technical committee by the Accellera organization in 2006, producing the first revision of the UPF specification, UPF 1.0 in 2007. Soon after UPF 1.0 release the group reformed under the IEEE organization as IEEE1801 with a major goal of merging in a competing standard, the Common Power Format (CPF). IEEE 1801 has since released three new versions of the UPF specification over the past ten years: IEEE1801-2009 (UPF 2.0), IEEE1801-2013 (UPF 2.1) and IEEE1801-2015 (UPF 3.0).

UPF solves some unique problems in the design world. One is the lack of any need to consider power supplies in traditional digital design at the RTL level (or higher). Others cope with the desire to separate what is supported by an IP component from what is actually implemented on a given chip. From an IP developer’s view: How can I provide one functional description and let my user choose what power features to use and how to implement them? From a chip architect’s view: How can I describe the power structure on a chip without having to embed the architecture into every block of the functional description? Continue reading “UPF Versioning Nightmare Solved”

Advancing Agile Hardware Design With Advanced Configurability

The concept of Agile design has been in practice for a long time.  Agile Software development is probably most universally practiced in part because a robust support ecosystem exists: from tool suppliers and consultants to the techniques new generations of software developers are taught in school.  If I narrow my focus to just the design phase of software development, I see it’s accepted as law that software design should be parameterized.  No matter what modern language you are using, you invoke a procedure by calling it and passing parameters to specify both data and control (options). With this design style, you can accept calls to use features that are specified, but not yet implemented. More importantly, it makes it easier to reuse the code in other designs or in other places in your design. Reuse is a key principle in applying Agile techniques in software design. Continue reading “Advancing Agile Hardware Design With Advanced Configurability”

Get Agile

Why a methodology for developing software is now required in hardware. History repeats itself, but frequently not in the exactly the same place. The problems faced by system engineering teams today rising complexity, shorter market windows and more issues involving interactions that affect everything from dynamic power and leakage current to electromigration and finFET design mirror the kinds of top-down issues that software developers began encountering more than two decades ago. Continue reading “Get Agile”

IP Is EDA

Earlier this month I had the distinct pleasure of attending the EDA Consortium’s (EDAC) prestigious Phil Kaufman award dinner. This year’s winner is Lucio Lanza, managing director of Lanza techVentures, LLC. Lucio is an EDA industry legend. We used to bump into each other often in the Cadence hallways after both of our companies had been acquired by Cadence around 1989. I truly appreciated Lucio’s leadership style with the Artisan board of directors when I was Vice President of Corporate Ventures there. Lucio’s strategic insights and steady pressure to keep us focused on the critical items were a major factor in Artisan’s success.

Continue reading “IP Is EDA”

Is IC Design Methodology at the Breaking Point

On Semiconductor Engineering, Randy Smith discusses the mounting evidence that traditional “waterfall” methods used to develop complex ICs are reaching the breaking point and discusses Agile software development methods to see what can be applied.

Continue reading “Is IC Design Methodology at the Breaking Point”