For those of you that have been reading my blogs or watching my presentations for a while, you will know I like to use cars for analogies. They represent a system that everyone understands at a user level, they are composed of many subsystems, the details of which can get pretty complicated if you dig deep. So today, you will see how most chip architectures are designed like having a car without a gas pedal – and what you can do about it. “Is Designing Your Chip Architecture Like Driving a Car with No Pedals?”
Recently I attended a presentation at the Machine Learning Developers Conference held at the Santa Clara Convention Center. The presentation, “Overcoming the Memory System Challenge in Dataflow Processing”, was given jointly by Darren Jones of Wave Computing and Drew Wingard of Sonics. The presentation was indeed fascinating as Jones first described how dataflow processors are ideal for deep learning, especially as compared to using existing CPU and GPU architectures. Jones then showed some performance numbers for machine learning training using the Wave Computing solution. And that is when I had to scratch my head. I did not hear any gasps. Everyone just accepted this phenomenal piece of engineering – just took it in stride. “Are Incredible Engineering Feats Treated As Commonplace Today?”
The concept of Agile design has been in practice for a long time. Agile Software development is probably most universally practiced in part because a robust support ecosystem exists: from tool suppliers and consultants to the techniques new generations of software developers are taught in school. If I narrow my focus to just the design phase of software development, I see it’s accepted as law that software design should be parameterized. No matter what modern language you are using, you invoke a procedure by calling it and passing parameters to specify both data and control (options). With this design style, you can accept calls to use features that are specified, but not yet implemented. More importantly, it makes it easier to reuse the code in other designs or in other places in your design. Reuse is a key principle in applying Agile techniques in software design. “Advancing Agile Hardware Design With Advanced Configurability”
Power management in IC design is loaded with exciting new developments. There have been attempts to solve power-related issues by altering the overall semiconductor process, biasing selected portions of a design, implementing various power distribution structures, introducing power gating, changing on chip network architectures, introducing microprocessor-based power channels, introducing energy processing units, and even more. Before jumping right into this topic, I think it’s best to provide an overview of what got us to this point. In future posts, I’ll delve more into the state of the art and the important trends affecting the future of power-efficient IC design. “The History of Power (Energy) Management in IC Design”
Make vs. buy isn’t as simple a decision as it might appear. When companies consider purchasing Semiconductor IP (SIP), they often have a strict procedure for evaluating third-party vendors and their products. If they don’t have a set way of evaluating IP, the Global Semiconductor Alliance (GSA) has developed a Hard IP Licensing Risk Assessment Tool to aid in assessing the value of IP (there is also a quality assessment tool). This aid is part of the GSA IP ecosystem Tool Suite and is complementary to the entire industry – regardless of member status within GSA. It is a great tool suite and many companies have similar methodologies they use when considering the purchase of SIP. “Don’t Forget To Consider Productivity In Semiconductor IP Evaluations”
Why a methodology for developing software is now required in hardware. History repeats itself, but frequently not in the exactly the same place. The problems faced by system engineering teams today rising complexity, shorter market windows and more issues involving interactions that affect everything from dynamic power and leakage current to electromigration and finFET design mirror the kinds of top-down issues that software developers began encountering more than two decades ago. “Get Agile”
There are four primary failure modes associated with NoCs. Recently, the reliability features of on-chip network (NoC) IP have received much attention. One reason for this focus has been the rush of companies to get into the automotive electronics market and the explosion of new automotive features being implemented in electronic systems. While the details may vary, the high-level view of on-chip network reliability is really quite simple. “NoC Reliability: Simplified”
Earlier this month I had the distinct pleasure of attending the EDA Consortium’s (EDAC) prestigious Phil Kaufman award dinner. This year’s winner is Lucio Lanza, managing director of Lanza techVentures, LLC. Lucio is an EDA industry legend. We used to bump into each other often in the Cadence hallways after both of our companies had been acquired by Cadence around 1989. I truly appreciated Lucio’s leadership style with the Artisan board of directors when I was Vice President of Corporate Ventures there. Lucio’s strategic insights and steady pressure to keep us focused on the critical items were a major factor in Artisan’s success.
On Semiconductor Engineering, Randy Smith discusses the mounting evidence that traditional “waterfall” methods used to develop complex ICs are reaching the breaking point and discusses Agile software development methods to see what can be applied.