The concept of Agile design has been in practice for a long time. Agile Software development is probably most universally practiced in part because a robust support ecosystem exists: from tool suppliers and consultants to the techniques new generations of software developers are taught in school. If I narrow my focus to just the design phase of software development, I see it’s accepted as law that software design should be parameterized. No matter what modern language you are using, you invoke a procedure by calling it and passing parameters to specify both data and control (options). With this design style, you can accept calls to use features that are specified, but not yet implemented. More importantly, it makes it easier to reuse the code in other designs or in other places in your design. Reuse is a key principle in applying Agile techniques in software design.
Is there a corollary in Agile hardware design? Are there languages and tools that support hardware design like there are in software design?
Hardware engineers have been expressing and sometimes using Agile methodologies for a number of years. There are several LinkedIn groups focused on Agile hardware development (see Agile IC Methodology) that combined have nearly a thousand members. Yet these engineers still do not have a lot of tools being developed to support their desire to use Agile in hardware design – or do they?
When it comes to making an integrated circuit (IC), we think about doing system, logic, or physical design. All of these design phases rely on tools, Electronic Design Automation (EDA) tools. But EDA tools are helping with more detailed tasks – and frankly mostly about logic and physical design. In order to implement Agile methodologies, most teams today are changing the workflow and not expecting much assistance on Agile implementation to come from the tools.
Doing system-level design is a bit like doing software development – reuse is a key principle in applying Agile techniques in hardware design.
Just like in software design, hardware design makes use of libraries to be able to use functions already developed by others (e.g., logic libraries, standard cell libraries, etc.). Commercial offerings of Semiconductor Intellectual Property (SIP) provide exactly this type of functionality. Some of these functions will have more options than others. A two-input NAND function has fixed, though useful, functionality. An SRAM memory compiler will usually support many memory configurations and options. The more parameterized functions supported, the more that function enables Agile-style designs.
The ultimate flexibility in support of Agile IC methodologies comes from the most sophisticated SIP providers such as those providing network-on-chip (NoC) IP. Companies such as Sonics are providing technology that is so flexible that the number of options available cannot be specified with just a few parameters. Instead a software environment is provided which allows the user to describe the blocks that should be connected, protocols used, signal priorities, target performance, and much, much more.
These environments collect the design variables and then compile the actual IP to be used in a specific implementation. In the same way that Agile software development places high value on early working prototypes, the NoC design environment enables SoC teams to quickly build functional prototypes of the NoC in the context of the SoC’s performance environment. This allows rapid exploration of performance-oriented choices and much faster architecture iteration – which are also recognizable Agile techniques. Beyond performance analysis, the NoC design environment also enables automated testing, synthesis and timing constraint generation, and power analysis. All of these help design teams reduce the time and effort needed to learn more about their SoC while there is still time to change it. Such re-factoring is another staple of Agile design.
Especially interesting is the new class of SIP introduced in the past year by Sonics – an energy processing unit (EPU). This brings Agile functionality to the implementation of energy savings techniques. Like Sonics’ NoC products, its EPU uses a development environment (EPU Studio). Again, the use of the EPU design environment enables earlier exploration and easier optimization of power partitioning and energy management approaches, together with rapid creation of the configured IP and the SoC power intent (in IEEE-1801 UPF). This is another powerful tool now available to Agile IC developers.
Applying Agile methodology to the challenges of implementing pervasive technology such as network on chip or energy (power) management is vastly improved by leveraging SIP which in itself is easily (re)configurable through the use of a powerful design environment. The use of this type of IP is becoming necessary to complete designs on time in today’s highly competitive markets.