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Free Trial Explores EPU IP and Automation

April 19, 2017 | Don Dingee
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Free Trial Explores EPU IP and Automation

Last summer at 53DAC in Austin, Sonics rolled out a seminar with a formative strategy for its Energy Processing Unit, or EPU. After that session, I summarized the idea in my SemiWiki blog:

“The premise of an EPU is that power savings using software, even in a dedicated microcontroller, is relatively slow, perhaps 50 to 500 times slower than what hardware-based power control can handle. Faster speeds mean narrower moments of idle time can be exploited to save energy, and distributed, autonomous, deadlock-free ICE-Grain controllers mean many more of those moments can be processed all over the system-on-chip (SoC) – leaving the CPU to do real work.”

There is some great material on the Sonics website going more into depth on the ICE-Grain Power Architecture and the recorded seminar presentation itself (registration required). The cornerstone of that presentation was a study of power savings in an implementation of the widely available Google G2 VP9 Decoder intellectual property (IP) block. With the ICE-Grain Power Architecture applied, a 94% energy reduction in 480i60 playback was uncovered. Sonics also went after a 2160p60 video pipeline looking for savings in line-oriented processing. In this scenario, power gating during “horizontal retrace” (HSYNC) idle moments of only 1.7 usec at hardware speeds saves 41% of the energy.

You’re probably thinking: that’s nice, Sonics has some super-cool hardware IP for energy management and knows how to optimize the heck out of one domain of IP blocks for that kind of power savings. What’s an average SoC designer with randomly selected IP blocks supposed to do? Or, how does the designer working under the “god” architect who is already heavily invested in an SoC power management architecture sell the idea of third-party distributed IP?

Well, I’m not from Sonics corporate, but I am here to help. If you’ve looked at the background on the Sonics site, you’ve probably surmised that ICE-Grain controllers are little chunks of configurable hardware with a simplified interconnect for easy timing closure across long distances. (We should point out that the EPU is not based on Sonics NoC IP optimized for data interconnect and throughput.)

Sonics recognized early on that without automation, designing their ICE-Grain IP into a large scale SoC could take a small army of people and months of effort. That’s why they invested in both the IP and a design automation tool to help deploy it. Behold, the EPU Studio Configuration Trial running in SonicsStudio Director:

5 reasons to go get the free EPU Studio Configuration Trial right now:

  • It’s Eclipse. You’re probably already using the Eclipse IDE somewhere in your EDA tool stack. Resize panes, move them, add and subtract until your environment fits your workflow.
  • It’s abstracted design. While it helps to understand UPF concepts, it’s not required to create an energy management solution. ICE-Grains are configured using tables and state transitions.
  • It’s scalable. The example in the configuration trial is small, but the tool supports ICE-Grain configurations with thousands of distributed grains working together.
  • It’s doable. It took me about 1 hour to install the demo and complete it. At each step, there is a verification check, and in most cases a picture showing what the result should look like.
  • It’s ready to go. The trial download is fully functional – its only limitation is a 2-week demo license. Designers can explore a more complex ICE-Grain configuration by setting up a self-guided project.

The configuration trial sets up one cluster of three grains just to illustrate the concepts of designing with the EPU IP. Following the demo, grain controllers are configured for a simple set of transitions between on, sleep, and doze using a transition matrix and an event selection table.

Trivial? Perhaps, from a first glance. The trial is supposed to show how easy working with EPU IP can be. Part of the idea is to orient designers who are used to creating UPF statements in a text editor, or worse yet blasting away in raw RTL to add logic, to a more visual toolset.

There’s more happening, however – a lot more. When completed, there are many views of the configuration that aren’t explicitly visited during the guided steps of the configuration trial. Out of curiosity, I clicked the Registers tab in the center window:

Right. This “trivial” demonstration creates 277 registers. Taking a closer look at the grayed-out fields shows many of these registers are read-only, saving substantial area. Still, a lot is going on under the hood. Imagine how many registers a bigger SoC power management configuration would have. Oh, wait – maybe you don’t have to imagine it, especially if you’ve ever tried to write power management software.

This is the biggest barrier to traditional SoC power management schemes: laying the hardware in is usually doable, but the software teams then spend the rest of their careers figuring out how to program all the transitions. Trying to change the scheme creates a huge mess, which is why that architecture “god” usually just overrules anyone even thinking of touching it.

A key point in all this: by default, an EPU operates independently from power management software – leading to many of the registers being read-only. Software can choose to interact with the EPU hardware, giving teams more control if they want it.

Large, well-established teams working on big SoC designs may be begging for a way forward as they press the limits of their power management architecture. Sonics’ CTO Drew Wingard says he’s working with such a team with 15 people doing power management alone, and two other design groups intertwined. It begs the question, can companies really continue to afford 15 people working on SoC power management, or can those 15 designers be put to better use adding value?

In the post-mobile world, including things like IoT devices, projects tend to be smaller and more numerous and chip variants need to be spun quickly. A consistent energy management architecture would help reach some of the more aggressive goals for always-on devices. These design groups may also be coming from a base of less experience with IP-based SoC design, perhaps realizing the limits of merchant microcontrollers and looking to optimize their devices for power consumption.

What SoC design team wouldn’t benefit from IP automation? EPU Studio is way more than a spiffy UI to just create a configuration. Sonics’ automation knows where all those auto-generated registers in the EPU IP live, and the required hardware sequencing to get the best results. Auto-generated IP means the time to the first working simulation is much faster. With automation, design teams have time to explore multiple energy management implementations and optimize more use cases.

Judge for yourself. Getting started is easy:

  • Visit any page on https://sonicsinc.com
  • Click the “Free Trial” button in the upper right corner.
  • Fill out the form and request a download of the EPU Studio Configuration Trial.
  • In an hour or maybe two, you’ll see the completed results and can explore what’s going on.
  • You can then try creating a more advanced configuration on your own.

Sonics has created a formidable competitive weapon for SoC teams with the EPU concept. Taking back battery power in those idle moments could be the difference maker for consumers considering a device. Freeing up teams from the drudgery of a software-based power management implementation is a huge plus. Exploration might be the biggest win – instead of rushing a best-guess attempt to the finish line, teams can really dive in and evaluate several energy management approaches to select the best one. It’s worth a shot just to get a look at the technology via this trial.

Behold the Intrinsic Value of IP

Understanding the intrinsic value of Intellectual Property is like beauty, it is in the eye of the beholder.  The beholder of IP Value is ultimately the user/consumer of that IP – the buyers. Buyers tend to value IP based upon their ability to utilize that IP to create competitive advantage, and therefore higher value for their end product. The IP Value figure above was created to capture this concept. Continue reading “Behold the Intrinsic Value of IP”

Advancing Agile Hardware Design With Advanced Configurability

The concept of Agile design has been in practice for a long time.  Agile Software development is probably most universally practiced in part because a robust support ecosystem exists: from tool suppliers and consultants to the techniques new generations of software developers are taught in school.  If I narrow my focus to just the design phase of software development, I see it’s accepted as law that software design should be parameterized.  No matter what modern language you are using, you invoke a procedure by calling it and passing parameters to specify both data and control (options). With this design style, you can accept calls to use features that are specified, but not yet implemented. More importantly, it makes it easier to reuse the code in other designs or in other places in your design. Reuse is a key principle in applying Agile techniques in software design. Continue reading “Advancing Agile Hardware Design With Advanced Configurability”

The History of Power (Energy) Management in IC Design

Power management in IC design is loaded with exciting new developments. There have been attempts to solve power-related  issues by altering the overall semiconductor process, biasing selected portions of a design, implementing various power distribution structures, introducing power gating, changing on chip network architectures, introducing microprocessor-based power channels, introducing energy processing units, and even more. Before jumping right into this topic, I think it’s best to provide an overview of what got us to this point.  In future posts, I’ll delve more into the state of the art and the important trends affecting the future of power-efficient IC design. Continue reading “The History of Power (Energy) Management in IC Design”

Everything is Here!

Doing business with Sonics has never been easier than in 2017. We just launched a re-designed web site that provides everything you need to know about our EPU and NoC technologies in a quick and easy to find format. Whether you are a power architect looking to save energy or an SoC designer searching for chip integration and interconnect solutions, we’ve crafted a thoughtful customer journey specifically for you. Our content-driven site takes you from understanding the problems associated with on-chip power management and chip integration through our products and solutions to serious consideration. Continue reading “Everything is Here!”

Got Energy?

Why everyone needs to start taking power more seriously, and what you can do about it.

Energy is a finite resource, which means it’s not someone else’s problem. It’s everyone’s problem.

This isn’t just another doom and gloom prediction. Energy consumption has been rising steadily for decades. Unfortunately, it has been increasing at a faster rate than energy production. A Semiconductor Industry Association report entitled, “Rebooting the IT Revolution: A Call to Action,” says we could run out of energy to power computers by 2040.

Continue reading “Got Energy?”

Welcome to our new website!

Thanks for visiting us. After 20 years of business success serving the on-chip communication needs of system architects and SoC designers, Sonics has turned its attention to the issue of power management. We have expanded our technology and product portfolio to address the critical issue of saving on-chip power. Every design team and engineer developing chips faces this challenge today, from expert power architects making their chips more efficient to those attempting to optimize their power architecture for the very first time. Continue reading “Welcome to our new website!”

NoC Versus PIN: Size Matters

Complexity and flexibility are the real drivers of fabric choice, not the number of initiators and targets. Since I first helped introduce the concept of applying networking techniques to address SoC integration challenges in 2007, I have been asked many hundreds of times how to determine when and where to best use an on-chip network (NoC) instead of a passive interconnect network (PIN)? Is there a minimum number of initiators and targets below which it makes more sense to use a PIN for the SoC architecture in “smaller” designs? Continue reading “NoC Versus PIN: Size Matters”

Don’t Forget To Consider Productivity In Semiconductor IP Evaluations

Make vs. buy isn’t as simple a decision as it might appear. When companies consider purchasing Semiconductor IP (SIP), they often have a strict procedure for evaluating third-party vendors and their products. If they don’t have a set way of evaluating IP, the Global Semiconductor Alliance (GSA) has developed a Hard IP Licensing Risk Assessment Tool to aid in assessing the value of IP (there is also a quality assessment tool). This aid is part of the GSA IP ecosystem Tool Suite and is complementary to the entire industry – regardless of member status within GSA. It is a great tool suite and many companies have similar methodologies they use when considering the purchase of SIP. Continue reading “Don’t Forget To Consider Productivity In Semiconductor IP Evaluations”

Get Agile

Why a methodology for developing software is now required in hardware. History repeats itself, but frequently not in the exactly the same place. The problems faced by system engineering teams today rising complexity, shorter market windows and more issues involving interactions that affect everything from dynamic power and leakage current to electromigration and finFET design mirror the kinds of top-down issues that software developers began encountering more than two decades ago. Continue reading “Get Agile”