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Best Practices for Power Management in SoCs Today

May 22, 2017 | Rich Wawrzyniak
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Best Practices for Power Management in SoCs Today

Interview with a Power Management Architect

Dynamic Power Management has become a ‘must-have’ in Systems-on-a-Chip (SoC) design today because of tightening power budgets and rising transistor counts. These increases mainly stem from evolving market requirements for more device functionality and richer feature sets being made available to meet changing market requirements. The semiconductor industry has responded with a plethora of different solutions to these issues.

Semico Research Corp. conducted an interview with Jawad Haj-Yihia, a Power Management Architect formerly of Intel Corp. in Israel. The following article represents key aspects of that interview delving into many of the issues that confront Power Management Architects in the industry today. Continue reading “Best Practices for Power Management in SoCs Today”

Are Incredible Engineering Feats Treated As Commonplace Today?

Recently I attended a presentation at the Machine Learning Developers Conference held at the Santa Clara Convention Center. The presentation, “Overcoming the Memory System Challenge in Dataflow Processing”, was given jointly by Darren Jones of Wave Computing and Drew Wingard of Sonics. The presentation was indeed fascinating as Jones first described how dataflow processors are ideal for deep learning, especially as compared to using existing CPU and GPU architectures. Jones then showed some performance numbers for machine leaning training using the Wave Computing solution. And that is when I had to scratch my head. I did not hear any gasps. Everyone just accepted this phenomenal piece of engineering – just took it in stride. Continue reading “Are Incredible Engineering Feats Treated As Commonplace Today?”

Free Trial Explores EPU IP and Automation

Last summer at 53DAC in Austin, Sonics rolled out a seminar with a formative strategy for its Energy Processing Unit, or EPU. After that session, I summarized the idea in my SemiWiki blog:

“The premise of an EPU is that power savings using software, even in a dedicated microcontroller, is relatively slow, perhaps 50 to 500 times slower than what hardware-based power control can handle. Faster speeds mean narrower moments of idle time can be exploited to save energy, and distributed, autonomous, deadlock-free ICE-Grain controllers mean many more of those moments can be processed all over the system-on-chip (SoC) – leaving the CPU to do real work.” Continue reading “Free Trial Explores EPU IP and Automation”

Behold the Intrinsic Value of IP

Understanding the intrinsic value of Intellectual Property is like beauty, it is in the eye of the beholder.  The beholder of IP Value is ultimately the user/consumer of that IP – the buyers. Buyers tend to value IP based upon their ability to utilize that IP to create competitive advantage, and therefore higher value for their end product. The IP Value figure above was created to capture this concept. Continue reading “Behold the Intrinsic Value of IP”

Advancing Agile Hardware Design With Advanced Configurability

The concept of Agile design has been in practice for a long time.  Agile Software development is probably most universally practiced in part because a robust support ecosystem exists: from tool suppliers and consultants to the techniques new generations of software developers are taught in school.  If I narrow my focus to just the design phase of software development, I see it’s accepted as law that software design should be parameterized.  No matter what modern language you are using, you invoke a procedure by calling it and passing parameters to specify both data and control (options). With this design style, you can accept calls to use features that are specified, but not yet implemented. More importantly, it makes it easier to reuse the code in other designs or in other places in your design. Reuse is a key principle in applying Agile techniques in software design. Continue reading “Advancing Agile Hardware Design With Advanced Configurability”

The History of Power (Energy) Management in IC Design

Power management in IC design is loaded with exciting new developments. There have been attempts to solve power-related  issues by altering the overall semiconductor process, biasing selected portions of a design, implementing various power distribution structures, introducing power gating, changing on chip network architectures, introducing microprocessor-based power channels, introducing energy processing units, and even more. Before jumping right into this topic, I think it’s best to provide an overview of what got us to this point.  In future posts, I’ll delve more into the state of the art and the important trends affecting the future of power-efficient IC design. Continue reading “The History of Power (Energy) Management in IC Design”

Everything is Here!

Doing business with Sonics has never been easier than in 2017. We just launched a re-designed web site that provides everything you need to know about our EPU and NoC technologies in a quick and easy to find format. Whether you are a power architect looking to save energy or an SoC designer searching for chip integration and interconnect solutions, we’ve crafted a thoughtful customer journey specifically for you. Our content-driven site takes you from understanding the problems associated with on-chip power management and chip integration through our products and solutions to serious consideration. Continue reading “Everything is Here!”

Got Energy?

Why everyone needs to start taking power more seriously, and what you can do about it.

Energy is a finite resource, which means it’s not someone else’s problem. It’s everyone’s problem.

This isn’t just another doom and gloom prediction. Energy consumption has been rising steadily for decades. Unfortunately, it has been increasing at a faster rate than energy production. A Semiconductor Industry Association report entitled, “Rebooting the IT Revolution: A Call to Action,” says we could run out of energy to power computers by 2040.

Continue reading “Got Energy?”

Welcome to our new website!

Thanks for visiting us. After 20 years of business success serving the on-chip communication needs of system architects and SoC designers, Sonics has turned its attention to the issue of power management. We have expanded our technology and product portfolio to address the critical issue of saving on-chip power. Every design team and engineer developing chips faces this challenge today, from expert power architects making their chips more efficient to those attempting to optimize their power architecture for the very first time. Continue reading “Welcome to our new website!”

NoC Versus PIN: Size Matters

Complexity and flexibility are the real drivers of fabric choice, not the number of initiators and targets. Since I first helped introduce the concept of applying networking techniques to address SoC integration challenges in 2007, I have been asked many hundreds of times how to determine when and where to best use an on-chip network (NoC) instead of a passive interconnect network (PIN)? Is there a minimum number of initiators and targets below which it makes more sense to use a PIN for the SoC architecture in “smaller” designs? Continue reading “NoC Versus PIN: Size Matters”