November 15, 2012
An interconnect IP vendor needs to be more than a single product company. Customers expect a complete portfolio of System IP products that meet all the connectivity needs of today’s complex SoCs along with the tools necessary to test and verify the system. This includes all the interconnect fabric topology structures, memory subsystems, security, power management and performance analysis tools needed to define and develop a complete on-chip communications network.
August 6, 2012
Designers defining the next generation SoCs are adding more cores in pursuit of the ever increasing user experience.
Whether for pace setting smart phones, WiFi routers, or personal medical devices, making all this IP work as intended in the SoC requires system IP. System IP includes the on-chip network, performance analysis tools, debug tools, power management and memory subsystems necessary for best in class SoCs. Whether used by the architect in the initial definition of the SoC or the layout engineer finalizing timing for place and route closure, system IP is critical to the design insuring that the capabilities of the SoC will meet the required end user experiences.
As the end user experiences drive SoC requirements, performance analysis of differing architecture choices allow SoC architects to choose the best configuration of the on-chip networks and the IP blocks. Defining the interaction of the few IP blocks driving key traffic as served by the available bandwidth is the first step. Based upon the market requirements, the memory system is mapped to DDR3/4, LPDDR2/3 and/or 3D TSV memory devices, defining an upper best case bandwidth available to the SoC to be shared across various IP cores. Having a high efficiency memory system supporting multiple transactions distributes memory bandwidth while providing the best overall performance (and battery life) in a multi-core SoC. Heterogeneous cores, e.g. CPU, graphics, DSP, rely upon the on chip network for efficient latency and bandwidth as multiple memory transactions are funneled into a shared memory subsystem.
August 1, 2012
Even though the cloud is permeating everything we do today, I was recently reminded that it’s even omnipresent far outside the walls of tech. With all the TV ads, as well as our most prominent airports and U.S. highways peppered with cloud-based billboards, even our parents know how to properly use cloud in sentence today. But to hear about the cloud from the pulpit at church on Sunday, that caught me a bit off guard. (And no, the punch line was not that heaven was in the clouds!)
A visiting homilist explained that he could travel light—especially to a high-tech place like Silicon Valley now that all his information was in the cloud and easily accessible from anywhere, anytime. It was true, he had no problem accessing his homily, until he tried to print and the printer ran out of ink. Unfortunately, the content was stuck in the cloud so he had to “wing it.” Needless to say, this quickly brings us back down to earth with a firm reminder that as powerful as the cloud is, at some point we are limited by the performance of (or lack thereof) our local devices.
Clearly our local devices are not much use without cloud con
June 29, 2012
Just how important are IP subsystems to complex SoC designs? It appears much more than you may have thought just a few months ago.
With the emergence of SoCs that now support the cloud computing revolution and every major cloud-connected device, SoC complexity is increasing at a dizzying pace. We commonly now see increasing number of IP cores, cores from multiple sources, different protocols and core frequencies, and so on. And of course, the growing challenges this level of complexity brings to SoC designers and their ability to execute a successful SoC program are also major considerations. So the answer to the above question drove an interesting panel discussion on the emergence and importance of IP subsystems at this month’s DAC.