August 6, 2012
Designers defining the next generation SoCs are adding more cores in pursuit of the ever increasing user experience.
Whether for pace setting smart phones, WiFi routers, or personal medical devices, making all this IP work as intended in the SoC requires system IP. System IP includes the on-chip network, performance analysis tools, debug tools, power management and memory subsystems necessary for best in class SoCs. Whether used by the architect in the initial definition of the SoC or the layout engineer finalizing timing for place and route closure, system IP is critical to the design insuring that the capabilities of the SoC will meet the required end user experiences.
As the end user experiences drive SoC requirements, performance analysis of differing architecture choices allow SoC architects to choose the best configuration of the on-chip networks and the IP blocks. Defining the interaction of the few IP blocks driving key traffic as served by the available bandwidth is the first step. Based upon the market requirements, the memory system is mapped to DDR3/4, LPDDR2/3 and/or 3D TSV memory devices, defining an upper best case bandwidth available to the SoC to be shared across various IP cores. Having a high efficiency memory system supporting multiple transactions distributes memory bandwidth while providing the best overall performance (and battery life) in a multi-core SoC. Heterogeneous cores, e.g. CPU, graphics, DSP, rely upon the on chip network for efficient latency and bandwidth as multiple memory transactions are funneled into a shared memory subsystem.