Introducing ICE-G1 EPU

The World’s First Energy Processing Unit

Based on the reprogrammable ICE-Grain Power Architecture, Sonics’ ICE-G1 Energy Processing Unit (EPU) aggregates both active and static power savings techniques into an automated methodology that users can scale and repeat from their first chip design to its derivatives to extract more savings through successive refinement. EPUs process millions of power state transitions per second (MSPS) in parallel, hundreds of times more than software-based approaches using dedicated microcontrollers, while delivering deterministic responsiveness.

EPU / CPU Ying Yang

Stop Wasting Energy and Leaving Power Savings on the Table

Chip designers waste too many energy-saving opportunities with conventional power management approaches because they can’t easily expose them, nor transition circuit states fast enough to take advantage of them. The ICE-G1 Energy Processing Unit (EPU) exploits circuit idle moments those periods of time when circuits are not needed for productive work to make power state transitions up to 500 times faster than conventional approaches while supporting simultaneous switching of an unlimited number of power grains.

The new metric for power management is millions of power states per second or MSPS. Like MIPS for measuring the performance of CPUs, MSPS provides a metric of performance for EPUs. ICE-G1 enables processing of many MSPS in every chip.

ICE-G1 is right for you, if:

  • you’re already using multiple power management techniques, but you would save more power if you could switch states faster, scale to support finer partitioning or more easily optimize your policies to match your applications. Learn More
  • you know you need to save power, but your schedules never seem long enough to explore aggressive power management. Learn More
  • you have maxed out what your EDA tools can do for automatic clock-gating, and now you need to find greater power savings. Learn More

Slashes Power in Every Chip

No matter your perspective or role, power reduction has become a primary objective for chip designs in almost every application and market. Power optimization at the architecture level is now a requirement, even for some chips that are “plugged in.” Download the ICE-G1 Product Brief