Dr. Susumu Kohyama Joins Sonics’ Advisory Board: New Advisory Board Member Brings Significant Semiconductor Experience – July 16, 2008

New SonicsSX™ SMART Interconnect™ Solution Solves Memory Performance Problem for High Quality, High Definition Video SoCs: Includes Interleaved Multichannel Technology™ That Operates Transparently to Hardware and Software – July 1, 2008

Sonics Eliminates Barriers To Multichannel Memory Management Industry Adoption With New Interleaved Multichannel Technology™ -- IMT™ Delivers High Performance with Low Overhead and Operates Transparently to Software and Hardware – July 1, 2008

Sonics Director of Software Development Scott Evans and Cadence Architect for IC Verification Neyaz Khan will co-present a paper titled “CPF Flow for Highly-Configurable Interconnect IP” at this year’s CDNLive on September 9. This informative talk is part of CDN Live Track Two, Functional Verification B, at 2:15-3pm at the San Jose Convention Center. To register to attend CDN Live, visit http://www.cadenceevents.com/cdnlive/na/controller.cfm?view=registration.overview.

Sonics CTO Drew Wingard will present a paper entitled “Achieving high-memory bandwidth for Cortex family-based high-quality, high-definition (HQHD) video SoCs using multiple DRAM channels” at the ARM Developers’ Conference on Thursday, October 9, 2008 at the Santa Clara Convention Center at 3:00pm in room 203. For more information about the ARM Developers’ Conference, visit http://www.rtcgroup.com/arm/2008/.

An inflection point in SoC architecture is emerging as a result of increased processing and memory performance requirements as well as the economic value of transitioning SoC architecture from single to multiple DRAM channels.

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