Articles tagged: 'sonics'
September 6, 2012
Verify this? No, New Jersey in me is not coming out. This is not a pejorative; it is simply a request and a question. It is a request by SoC designers to the verification team. It is also the verification’s team response when they realize the enormity of the task: “You want me to verify this?”
As I continue the discussion on the use of System IP for SoC design, one of the less glamorous or often forgotten tasks of the SoC design is verification. There has been much discussion on how the demands from both the consumer and cloud infrastructure markets are driving SoC complexity, so I will not elaborate here. It is enough to say, that as the number of individual IP cores and subsystems increase, with a mix of IP from third parties along with internally developed IP, the task of verifying the functionality of individual IP blocks, subsystems and the end-to-end system is providing new challenges for verification teams.
August 6, 2012
Designers defining the next generation SoCs are adding more cores in pursuit of the ever increasing user experience.
Whether for pace setting smart phones, WiFi routers, or personal medical devices, making all this IP work as intended in the SoC requires system IP. System IP includes the on-chip network, performance analysis tools, debug tools, power management and memory subsystems necessary for best in class SoCs. Whether used by the architect in the initial definition of the SoC or the layout engineer finalizing timing for place and route closure, system IP is critical to the design insuring that the capabilities of the SoC will meet the required end user experiences.
As the end user experiences drive SoC requirements, performance analysis of differing architecture choices allow SoC architects to choose the best configuration of the on-chip networks and the IP blocks. Defining the interaction of the few IP blocks driving key traffic as served by the available bandwidth is the first step. Based upon the market requirements, the memory system is mapped to DDR3/4, LPDDR2/3 and/or 3D TSV memory devices, defining an upper best case bandwidth available to the SoC to be shared across various IP cores. Having a high efficiency memory system supporting multiple transactions distributes memory bandwidth while providing the best overall performance (and battery life) in a multi-core SoC. Heterogeneous cores, e.g. CPU, graphics, DSP, rely upon the on chip network for efficient latency and bandwidth as multiple memory transactions are funneled into a shared memory subsystem.
February 23, 2012
As the fabless era disaggregated EDA and IP offerings, there are areas where in- house development is still the norm, even with today’s $2.5B IP industry. One of these is on-chip network – connecting the IP cores and memory subsystem. On-chip interconnect or networks-on-chip (NoCs), in many companies, is still regarded as a part of …
September 26, 2011
System-Level Design recently interviewed Sonics CEO, Grant Pierce, about the future SoC design.