Articles tagged: 'performance'
January 31, 2013
If I can boil all this this data down, the ‘CES effect’ on the SoC world is the need for more performance, higher complexity and longer usage per charge (lower power). This should not be a big surprise to anyone tracking the SoC market. The consumer’s demand for all these high-tech gadgets is unrelenting and the pace of SoC development is not letting up anytime soon. I also could add to the list lower SoC cost (both development and product cost) and better execution (TTM). To keep up this pace, contributions are needed from all parts of the semiconductor ecosystem including better IP, improved system architecture and analysis tools.
September 27, 2012
Now that the iPhone 5 hype is quieting down, the discussion has turned to the A6 chip that is powering this must-have device. There is much speculation on what is inside the A6 processor. Is it a dual-core A15 or a custom architecture? Is it a ‘big.LITTLE’ architecture? What speed are cores running at—1.2GHz? Others argue that the graphics processor is of equal importance to the CPU for the overall user experience. In any case, Apple is boasting a 2x performance improvement over the previous generation iPhone.
This discussion, as expected, has expanded to rival CPUs like Qualcomm’s custom Krait core, used in Snapdragon, or Intel’s Atom processor. With all the talk of the processor performance (CPU and GPU), I found it interesting that there was only one brief reference to the memory architecture of the A6. At MemCon last week during the keynote presentation by Martin Lund, senior vice president at Cadence, mentioned the importance of ‘compute, interconnect and storage.’ He then continued on to discuss the time and energy engineering teams spend optimizing the memory interface to minimize latency. Of course at a memory conference we expect the focus to be on the memory, but the point is well taken. The CPU is only one part of the equation.
August 6, 2012
Designers defining the next generation SoCs are adding more cores in pursuit of the ever increasing user experience.
Whether for pace setting smart phones, WiFi routers, or personal medical devices, making all this IP work as intended in the SoC requires system IP. System IP includes the on-chip network, performance analysis tools, debug tools, power management and memory subsystems necessary for best in class SoCs. Whether used by the architect in the initial definition of the SoC or the layout engineer finalizing timing for place and route closure, system IP is critical to the design insuring that the capabilities of the SoC will meet the required end user experiences.
As the end user experiences drive SoC requirements, performance analysis of differing architecture choices allow SoC architects to choose the best configuration of the on-chip networks and the IP blocks. Defining the interaction of the few IP blocks driving key traffic as served by the available bandwidth is the first step. Based upon the market requirements, the memory system is mapped to DDR3/4, LPDDR2/3 and/or 3D TSV memory devices, defining an upper best case bandwidth available to the SoC to be shared across various IP cores. Having a high efficiency memory system supporting multiple transactions distributes memory bandwidth while providing the best overall performance (and battery life) in a multi-core SoC. Heterogeneous cores, e.g. CPU, graphics, DSP, rely upon the on chip network for efficient latency and bandwidth as multiple memory transactions are funneled into a shared memory subsystem.
June 25, 2012
From his presentation April 10, 2012, at the Design and Reuse IP-SoC Days conference in Santa Clara, Jack Browne, Sr. VP of Sales and Marketing at Sonics, discusses IPs increasing importance in the semiconductor value chain: