October 25, 2012
I was a bit frustrated this weekend after installing a digital light timer—yes a light timer. As an engineer this should be no big deal, and for the most part, I installed it without shocking myself or other major problems. This timer had all the bells and whistles. It knows about time zones, adjusts daily for dawn and dusk. It even adjusts for daylight savings time. The problem came when I tried to program this device. It took me two days to get it right (I actually had to read the instructions)! How did a very simple function like a switch become so complicated? I had a similar thought last week as discussions have intensified around the need for embedded consumer SoCs to support hardware cache coherency. How did connecting one core to another (a switch and router) become so complicated? Much of the discussion has been sparked with the recent introduction of the new ARM CCN-504 cache coherent interconnect. Although this IP is for high-end computing platforms, it is clear that these types of coherent networks will be needed for lower-performance applications also. It’s not that cache coherency is new in embedded SoCs. It has been used in computing clusters for some time now. Keeping memory coherency within the computing cluster, however, has been the problem of the CPU vendor only because it did not affect other memory transactions in the system. What is new is that other processors in the system (GPUs and DSPs) also will need coherent access to memory.