Articles tagged: 'GHz'
March 1, 2013
The market will force the SoC manufactures to get much more aggressive about power management. The J.D. Power report indicated that smart phone owners who are highly satisfied with their device’s battery life are more likely to repurchase the same brand of smart phone, so better power management is now a real competitive issue. Current SoC leaders must make it a priority to innovate around power management, implementing much more aggressive power saving techniques—or they run the risk of leaving the door wide open for competitors.
December 19, 2012
SoC design continues to challenge semiconductor and system companies in their pursuit to create a better user experience for a wide range of products. Given this, I was pleasantly surprised to see that two of the “Ten technologies that will change the world in 2013,” according to EETimes (December 2012 issue) were SoC-related.
September 27, 2012
Now that the iPhone 5 hype is quieting down, the discussion has turned to the A6 chip that is powering this must-have device. There is much speculation on what is inside the A6 processor. Is it a dual-core A15 or a custom architecture? Is it a ‘big.LITTLE’ architecture? What speed are cores running at—1.2GHz? Others argue that the graphics processor is of equal importance to the CPU for the overall user experience. In any case, Apple is boasting a 2x performance improvement over the previous generation iPhone.
This discussion, as expected, has expanded to rival CPUs like Qualcomm’s custom Krait core, used in Snapdragon, or Intel’s Atom processor. With all the talk of the processor performance (CPU and GPU), I found it interesting that there was only one brief reference to the memory architecture of the A6. At MemCon last week during the keynote presentation by Martin Lund, senior vice president at Cadence, mentioned the importance of ‘compute, interconnect and storage.’ He then continued on to discuss the time and energy engineering teams spend optimizing the memory interface to minimize latency. Of course at a memory conference we expect the focus to be on the memory, but the point is well taken. The CPU is only one part of the equation.
August 6, 2012
Designers defining the next generation SoCs are adding more cores in pursuit of the ever increasing user experience.
Whether for pace setting smart phones, WiFi routers, or personal medical devices, making all this IP work as intended in the SoC requires system IP. System IP includes the on-chip network, performance analysis tools, debug tools, power management and memory subsystems necessary for best in class SoCs. Whether used by the architect in the initial definition of the SoC or the layout engineer finalizing timing for place and route closure, system IP is critical to the design insuring that the capabilities of the SoC will meet the required end user experiences.
As the end user experiences drive SoC requirements, performance analysis of differing architecture choices allow SoC architects to choose the best configuration of the on-chip networks and the IP blocks. Defining the interaction of the few IP blocks driving key traffic as served by the available bandwidth is the first step. Based upon the market requirements, the memory system is mapped to DDR3/4, LPDDR2/3 and/or 3D TSV memory devices, defining an upper best case bandwidth available to the SoC to be shared across various IP cores. Having a high efficiency memory system supporting multiple transactions distributes memory bandwidth while providing the best overall performance (and battery life) in a multi-core SoC. Heterogeneous cores, e.g. CPU, graphics, DSP, rely upon the on chip network for efficient latency and bandwidth as multiple memory transactions are funneled into a shared memory subsystem.