September 6, 2012
As featured in:
Verify this? No, New Jersey in me is not coming out. This is not a pejorative; it is simply a request and a question. It is a request by SoC designers to the verification team. It is also the verification’s team response when they realize the enormity of the task: “You want me to verify this?”
As I continue the discussion on the use of System IP for SoC design, one of the less glamorous or often forgotten tasks of the SoC design is verification. There has been much discussion on how the demands from both the consumer and cloud infrastructure markets are driving SoC complexity, so I will not elaborate here. It is enough to say, that as the number of individual IP cores and subsystems increase, with a mix of IP from third parties along with internally developed IP, the task of verifying the functionality of individual IP blocks, subsystems and the end-to-end system is providing new challenges for verification teams.
There are several aspects of verification, including functional verification and performance verification. Functional verification includes connectivity testing and IP integration. Performance verification includes many aspects of overall system testing such as speed, power and bandwidth for various use cases. Both types of verification are important and necessary in today’s complex SoC, but for now I will focus on the functional verification and save performance verification for another blog.
Over the last few years as device complexity grew, SoC designers discovered that a large percentage of chip bugs often were found in their internally developed system interconnect. Individual IP blocks from trusted sources were tested and verified (which is good), but when connecting these blocks to the system, errors occurred due to protocol mismatches or corner cases that were difficult to anticipate. This problem (among others) facilitated the use of on-chip network system IP as a solution.
Having the interconnect as a well-defined IP block (IP generator to be precise) allowed a ‘correct-by-construction’ methodology by defining a standard protocol interface or ‘socket’ for each core in the system. These sockets then can be verified based on the interface protocol, either standard or proprietary, with protocol checkers. It is expected today that the on-chip network IP ships with protocol checkers and test benches for standard protocols such as AMBA (AXI3/4) and OCP. It is also expected that the test environment be open and flexible enough integrate custom protocol checkers developed by the customer.
Is this enough? The use of on-chip network system IP with a socket interface for the most part has solved or reduced many of the connectivity errors, thereby giving designers confidence with unit level verification. The challenge facing the verification team now is how to test connectivity and functionality at the system level when they have multiple levels of networks. A subsystem, or groups of IP blocks for specific functions, has its own on-chip network, which then is connected to higher levels of the on-chip network at the system level (networks embedded in networks). Clearly a standardized methodology is needed to keep the task of verifying all this IP from spinning out of control.
UVM (Universal Verification Methodology) is an industry standard methodology that helps designers meet this challenge by allowing them to leverage and re-use verification infrastructure that is already in place from IP vendors. UVM provides the necessary hooks to connect IP-specific ports or interfaces, thus creating the verification infrastructure used to perform functional verification of IP that can be re-used at the subsystem and SoC levels. Passive monitors, scoreboard components and functional coverage modules can be re-used for SoC/subsystem verification. With UVM infrastructure, building a complete verification environment for an SoC containing multiple IPs is a task that now becomes cost-effective in terms of time and effort.
With complexity of SoCs growing exponentially and time to market shrinking, any reuse of verification infrastructure from IP vendors can help to speed-up SoC delivery, which is critical for SoC product execution. Having system IP that includes a UVM verification infrastructure removes “shock and awe” from the verification team at having to create their own infrastructure. Now when asked to “verify this” they can simply reply, “no problem.”
–Frank Ferro is Director of Marketing at Sonics.