Making IP work and getting the right SoC!
August 6, 2012
As featured in:
Designers defining the next generation SoCs are adding more cores in pursuit of the ever increasing user experience. Whether for pace setting smart phones, WiFi routers, or personal medical devices, making all this IP work as intended in the SoC requires system IP. System IP includes the on-chip network, performance analysis tools, debug tools, power management and memory subsystems necessary for best in class SoCs. Whether used by the architect in the initial definition of the SoC or the layout engineer finalizing timing for place and route closure, system IP is critical to the design insuring that the capabilities of the SoC will meet the required end user experiences.
As the end user experiences drive SoC requirements, performance analysis of differing architecture choices allow SoC architects to choose the best configuration of the on-chip networks and the IP blocks. Defining the interaction of the few IP blocks driving key traffic as served by the available bandwidth is the first step. Based upon the market requirements, the memory system is mapped to DDR3/4, LPDDR2/3 and/or 3D TSV memory devices, defining an upper best case bandwidth available to the SoC to be shared across various IP cores. Having a high efficiency memory system supporting multiple transactions distributes memory bandwidth while providing the best overall performance (and battery life) in a multi-core SoC. Heterogeneous cores, e.g. CPU, graphics, DSP, rely upon the on chip network for efficient latency and bandwidth as multiple memory transactions are funneled into a shared memory subsystem.
Efficiently using the memory bandwidth – specifically, minimizing wasted cycles, is fundamental to the end user experience with best performance, best power and system cost benefits. In the broad range of system benchmarks, latency to main memory may impact, for example, the speed of internet browsing – clearly having a direct impact on the user experience. Extensive performance analysis is enabled as the System IP is aware of all traffic to/from all IP blocks and traffic can be analyzed for best results. Since every heterogeneous core has a role in the system performance, Quality of Sevice (QoS) tuning eases implementation of the architect’s intent with demonstrable results even as the number of cores scale.
Designers defining the next generation SoCs are adding more cores in pursuit of the ever increasing user experience.
As the architects finish with key system definition, then IP acquisition and integration activities increase with the ongoing design work of integrating the entire SoC. For complex SoCs over 100 IP blocks may be included in a design. Choices can be tough, with over a hundred IP vendors offering solutions, each with multiple products. The System IP eases the design burden by supporting both IP blocks and subsystems with the necessary broad range of interface protocols, widths, frequency domains and power domains.
System IP eases the challenges of maintaining a common software platform over multiple generations of SoC’s, built with varying IP cores and subsystems. Market research firm Semico, forecasts subsystem functions for computing, memory, video, communications, multimedia, security and system resource management. The increased abstraction from subsystems gives productivity benefit (leveraging use of commercial IP blocks) as well as differentiation through the integration of in-house IP blocks with standard industry IP blocks into reusable subsystems. A computing subsystem example would be ARM’s big.LITTLE CPU clusters where ARM does most of the integration ahead of time with the designer doing final configuration of features and/or number of cores. Another example would be faster communication subsystems like LTE advanced subsystems. By customizing a 4G LTE advanced subsystem solution with internal technology, SoC design teams can differentiate from standard IP blocks using their internal expertise while leveraging the shared R&D benefits of merchant 4G IP subsystems.
With the increasing cost of today’s SoCs, many are designed for multiple markets where not all of the functionality of the SoC is in use. Many also have multiple usage scenarios within a given market, e.g. music playback on our smartphone. With the importance of battery life, managing the power of a SoC, including the ability to power off unused blocks, gives the best battery life. Today’s 28nm SoCs are using dozens of power domains and even more clock domains to meet the performance and battery life requirements. By moving to system IP supporting hardware centric control of power transitions, end users will make more use of Dark Silicon (normally powered off) for better battery life as compared to interrupt centric software power management control.
When starting a new SoC design, your choice of system IP is a key early decision as you have now selected the on-chip network, performance analysis tools, debug tools, power management and memory subsystems available for your design. Making the right choice can provide a 2x benefit over other choices with regard to performance, power and cost, so make an informed choice.
–Jack Browne is Vice President of Marketing at Sonics, Inc.