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Taking Energy Back from Next-Generation MCU Designs

June 13, 2017 | Don Dingee
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Taking Energy Back from Next-Generation MCU Designs

Microamp-per-megahertz thinking served the microcontroller (MCU) community well for decades. As the focus shifts to connectivity and always-on use cases, bigger cores and wireless IP blocks push energy use in the wrong direction. Next-generation MCUs can ill afford to spend more energy just to manage themselves. Any mandatory software to make an MCU run usually frustrates customers considering design-ins. How does the MCU ecosystem manage energy moving forward?

From beginnings as register-oriented compute nuggets, MCUs grew bigger cores and wider data paths backed by higher resolution A/D and D/A peripherals. The “work hard, sleep harder” philosophy debuted. By waking up and performing computations as quickly as possible, then getting back to sleep, overall duty cycle is reduced and energy saved. A low duty cycle driven by software has its limits, however; it can cost more energy just to wake up and shut down a processor core than it takes to sample a sensor.

An “MCU-on-steroids” slims heterogeneous multicore architectures derived from mobile application processor designs, seeking a cost and power consumption profile MCU customers can accept. With more DMA-capable I/O cores in play, designers often turn to network-on-chip (NoC) IP, solving integration and multi-rate, multi-protocol challenges. NoC-based designs enable easier partitioning of interconnect logic into the MCU power architecture, greatly reducing the gate count in the “always on” portion of the design. A NoC-based approach also helps designers spin more MCU variants quickly.

Most advanced MCU designers still start by choosing the lowest-power processor core, occasionally with DVFS support, and parsing IP blocks into clock and power gated domains. Efficient cores, interconnect, and gating only go so far against stringent ultra-low power goals for most IoT and wearable applications operating on battery power or energy harvesting technology. Microamps-per-megahertz is an incomplete metric now, where crucial work in the MCU is often occurring outside of the processing core.

With power consumption being left in the lurch, the MCU design pendulum is swinging back to energy management, but with a huge plot twist: little or no software involved. In most mobile SoC designs, software-based schemes controlled by sophisticated operating systems sequence power carefully. For MCU design-ins, either compact RTOSes or bare metal programming are the norm. Forcing users to write their own code to sequence power states for hardware that they didn’t design is a bad idea.

Next-generation MCU with Sonics EPU for hardware-based energy management

What is the right approach in taking energy back from next-generation MCU designs? More and more MCU designers are now discovering energy management hardware IP, opening new possibilities. Sonics’ Energy Processing Unit (EPU) can exploit idle moments – in an IoT protocol, or a sensor processing algorithm, or a control loop – up to 500x faster and with far finer granularly than is possible with software.

To date, Sonics has mostly focused on the mobile SoC design problem, where teams have hit the limits of software-based power management. EPU IP technology may be an even better fit for MCU chip manufacturers and application developers using MCUs. How does this look in an MCU context?

  • Distributed energy management – EPU architecture distributes hardware controllers across the different power grains of the MCU using a timing-friendly fabric driven by centralized sequencers. Instead of brute force power and clock gating by programmable registers, automated design tools put the ICE-Grain IP to work without power management experts and months of effort.
  • Low overhead – EPU architecture is autonomous, and runs completely independently of the highest power digital components in an advanced MCU: the processor core – and its memories. This means energy management can be active chip-wide while the processor core is powered down. Reacting to sensor inputs without waking the processor is a huge win.
  • More designs, less time – MCU designers want flexibility, and packages and pins matter. They spin variants rapidly, cutting peripherals in and out creating exact fits for an application. Configurability wreaks havoc on a software-based power management scheme with inter-dependent sequencing, but is no problem for EPU hardware IP that directly captures such constraints.
  • Use case exploration – A sticking point is optimizing the energy control approach in critical use cases. Thoroughly and completely evaluating just a couple use cases MCU-wide can be months of effort when power management is complex. EPU architecture lends itself to rapid exploration with automation in play, which means more use cases can be optimized quickly.

Clusters implement high-level power states and transitionsWhat I see in working with EPU IP technology are two opportunities for deeper optimization of MCU designs, far beyond what conventional methods achieve.

First is the concept of clusters, grains managed together with a controller to implement a set of user-defined high-level power states and transitions. EPU designs are specified using EDA tools generating an optimized IP configuration from diagrams and tables. Clusters can bring system-level power management to life, easily visualized and automatically verified.

Second is exploiting the short but numerous idle moments that live in-between active moments in an algorithm. Traditionally, MCU users are forced to make power decisions based on operating modes at the millisecond level or slower; functions are gated on or off depending on system needs. The EPU IP offers far finer granularity, both in space and time. A breakthrough case study decomposed the Google G2 VP9 Decoder IP block, snatching 94% of the overall energy from 480i60 playback with EPU IP inserted.

How much energy is locked inside a bursty IoT protocol, or MEMS sensor sampling, or a low-power display? Idle moments exist, with required digital IP blocks fully on only because turning them off and back on takes too long – using the processor and software. (Analog blocks with settling time can be trickier.) With hardware IP doing energy management, off/on timing shrinks drastically, perhaps 50 to 500 times, and finer grains expose more and longer idle moments to control.

Ready for a first-hand look at EPU IP technology? Click the “Free Trial” button in the upper right corner, or look at my previous post walking through the EPU Studio Configuration Trial.

It’s time to break away from the core-level power management trap that limits what MCUs can achieve. For IoT and wearable devices to succeed with consumers, the industry needs more than incremental MCU power management improvements. Sonics EPU IP technology takes the task of energy management from a team of highly specialized hardware and software designers to an intermediate (or experienced) functional designer who needn’t worry about power management details. Cracking the code – literally, with a hardware-based implementation – will lead to breakthrough MCU products using far less energy.

Best Practices for Power Management in SoCs Today

Interview with a Power Management Architect

Dynamic Power Management has become a ‘must-have’ in Systems-on-a-Chip (SoC) design today because of tightening power budgets and rising transistor counts. These increases mainly stem from evolving market requirements for more device functionality and richer feature sets being made available to meet changing market requirements. The semiconductor industry has responded with a plethora of different solutions to these issues.

Semico Research Corp. conducted an interview with Jawad Haj-Yihia, a Power Management Architect formerly of Intel Corp. in Israel. The following article represents key aspects of that interview delving into many of the issues that confront Power Management Architects in the industry today. Continue reading “Best Practices for Power Management in SoCs Today”

Are Incredible Engineering Feats Treated As Commonplace Today?

Recently I attended a presentation at the Machine Learning Developers Conference held at the Santa Clara Convention Center. The presentation, “Overcoming the Memory System Challenge in Dataflow Processing”, was given jointly by Darren Jones of Wave Computing and Drew Wingard of Sonics. The presentation was indeed fascinating as Jones first described how dataflow processors are ideal for deep learning, especially as compared to using existing CPU and GPU architectures. Jones then showed some performance numbers for machine learning training using the Wave Computing solution. And that is when I had to scratch my head. I did not hear any gasps. Everyone just accepted this phenomenal piece of engineering – just took it in stride. Continue reading “Are Incredible Engineering Feats Treated As Commonplace Today?”

Free Trial Explores EPU IP and Automation

Last summer at 53DAC in Austin, Sonics rolled out a seminar with a formative strategy for its Energy Processing Unit, or EPU. After that session, I summarized the idea in my SemiWiki blog:

“The premise of an EPU is that power savings using software, even in a dedicated microcontroller, is relatively slow, perhaps 50 to 500 times slower than what hardware-based power control can handle. Faster speeds mean narrower moments of idle time can be exploited to save energy, and distributed, autonomous, deadlock-free ICE-Grain controllers mean many more of those moments can be processed all over the system-on-chip (SoC) – leaving the CPU to do real work.” Continue reading “Free Trial Explores EPU IP and Automation”

Behold the Intrinsic Value of IP

Understanding the intrinsic value of Intellectual Property is like beauty, it is in the eye of the beholder.  The beholder of IP Value is ultimately the user/consumer of that IP – the buyers. Buyers tend to value IP based upon their ability to utilize that IP to create competitive advantage, and therefore higher value for their end product. The IP Value figure above was created to capture this concept. Continue reading “Behold the Intrinsic Value of IP”

Advancing Agile Hardware Design With Advanced Configurability

The concept of Agile design has been in practice for a long time.  Agile Software development is probably most universally practiced in part because a robust support ecosystem exists: from tool suppliers and consultants to the techniques new generations of software developers are taught in school.  If I narrow my focus to just the design phase of software development, I see it’s accepted as law that software design should be parameterized.  No matter what modern language you are using, you invoke a procedure by calling it and passing parameters to specify both data and control (options). With this design style, you can accept calls to use features that are specified, but not yet implemented. More importantly, it makes it easier to reuse the code in other designs or in other places in your design. Reuse is a key principle in applying Agile techniques in software design. Continue reading “Advancing Agile Hardware Design With Advanced Configurability”

The History of Power (Energy) Management in IC Design

Power management in IC design is loaded with exciting new developments. There have been attempts to solve power-related issues by altering the overall semiconductor process, biasing selected portions of a design, implementing various power distribution structures, introducing power gating, changing on chip network architectures, introducing microprocessor-based power channels, introducing energy processing units, and even more. Before jumping right into this topic, I think it’s best to provide an overview of what got us to this point.  In future posts, I’ll delve more into the state of the art and the important trends affecting the future of power-efficient IC design. Continue reading “The History of Power (Energy) Management in IC Design”

Everything is Here!

Doing business with Sonics has never been easier than in 2017. We just launched a re-designed web site that provides everything you need to know about our EPU and NoC technologies in a quick and easy to find format. Whether you are a power architect looking to save energy or an SoC designer searching for chip integration and interconnect solutions, we’ve crafted a thoughtful customer journey specifically for you. Our content-driven site takes you from understanding the problems associated with on-chip power management and chip integration through our products and solutions to serious consideration. Continue reading “Everything is Here!”

Got Energy?

Why everyone needs to start taking power more seriously, and what you can do about it.

Energy is a finite resource, which means it’s not someone else’s problem. It’s everyone’s problem.

This isn’t just another doom and gloom prediction. Energy consumption has been rising steadily for decades. Unfortunately, it has been increasing at a faster rate than energy production. A Semiconductor Industry Association report entitled, “Rebooting the IT Revolution: A Call to Action,” says we could run out of energy to power computers by 2040.

Continue reading “Got Energy?”

Welcome to our new website!

Thanks for visiting us. After 20 years of business success serving the on-chip communication needs of system architects and SoC designers, Sonics has turned its attention to the issue of power management. We have expanded our technology and product portfolio to address the critical issue of saving on-chip power. Every design team and engineer developing chips faces this challenge today, from expert power architects making their chips more efficient to those attempting to optimize their power architecture for the very first time. Continue reading “Welcome to our new website!”