Sonics Inc. Blog

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Welcome to our new website!

December 19, 2016 | Grant Pierce
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Got Energy?

Why everyone needs to start taking power more seriously, and what you can do about it.

Energy is a finite resource, which means it’s not someone else’s problem. It’s everyone’s problem.

This isn’t just another doom and gloom prediction. Energy consumption has been rising steadily for decades. Unfortunately, it has been increasing at a faster rate than energy production. A Semiconductor Industry Association report entitled, “Rebooting the IT Revolution: A Call to Action,” says we could run out of energy to power computers by 2040.

So what can we do about it? There are ways to save power significant amounts of energy at the system component and sub-system level. The National Resources Defense Council recently published its report, “Slashing Energy Use in Computers and Monitors While Protecting Our Wallets, Health, and Planet,” which states that keeping computers running takes the equivalent of 30 large power plants. The real problem, according to the report, is that power is wasted when computers sit idle—particularly the ones that are plugged into the wall. The group argues that implementing new standards could save U.S. consumers $3 billion a year.

It’s not just computers, though. All electronics can benefit from better energy management. Just as cars idling in traffic burn fuel, so do electronics. And as more devices are added, particularly those that are always on, the more energy will be wasted.

So where do you stand on power? Semico Research and Sonics are conducting a survey to better understand today’s status quo and tomorrow’s trends for power management best practices among chip design teams in semiconductor and electronic systems companies.

Please weigh in. Click here, or go to to take a short survey. Survey respondent data will be kept strictly confidential. The purpose of this industry survey is to understand how chip designers are managing power consumption and contrast that with expected future best practices. Sonics and Semico Research will publish results on their web sites.


Welcome to our new website!

Thanks for visiting us. After 20 years of business success serving the on-chip communication needs of system architects and SoC designers, Sonics has turned its attention to the issue of power management. We have expanded our technology and product portfolio to address the critical issue of saving on-chip power. Every design team and engineer developing chips faces this challenge today, from expert power architects making their chips more efficient to those attempting to optimize their power architecture for the very first time. Continue reading “Welcome to our new website!”

NoC Versus PIN: Size Matters

Complexity and flexibility are the real drivers of fabric choice, not the number of initiators and targets. Since I first helped introduce the concept of applying networking techniques to address SoC integration challenges in 2007, I have been asked many hundreds of times how to determine when and where to best use an on-chip network (NoC) instead of a passive interconnect network (PIN)? Is there a minimum number of initiators and targets below which it makes more sense to use a PIN for the SoC architecture in “smaller” designs? Continue reading “NoC Versus PIN: Size Matters”

Don’t Forget To Consider Productivity In Semiconductor IP Evaluations

Make vs. buy isn’t as simple a decision as it might appear. When companies consider purchasing Semiconductor IP (SIP), they often have a strict procedure for evaluating third-party vendors and their products. If they don’t have a set way of evaluating IP, the Global Semiconductor Alliance (GSA) has developed a Hard IP Licensing Risk Assessment Tool to aid in assessing the value of IP (there is also a quality assessment tool). This aid is part of the GSA IP ecosystem Tool Suite and is complementary to the entire industry – regardless of member status within GSA. It is a great tool suite and many companies have similar methodologies they use when considering the purchase of SIP. Continue reading “Don’t Forget To Consider Productivity In Semiconductor IP Evaluations”

Get Agile

Why a methodology for developing software is now required in hardware. History repeats itself, but frequently not in the exactly the same place. The problems faced by system engineering teams today rising complexity, shorter market windows and more issues involving interactions that affect everything from dynamic power and leakage current to electromigration and finFET design mirror the kinds of top-down issues that software developers began encountering more than two decades ago. Continue reading “Get Agile”

NoC Reliability: Simplified

There are four primary failure modes associated with NoCs. Recently, the reliability features of on-chip network (NoC) IP have received much attention. One reason for this focus has been the rush of companies to get into the automotive electronics market and the explosion of new automotive features being implemented in electronic systems. While the details may vary, the high-level view of on-chip network reliability is really quite simple. Continue reading “NoC Reliability: Simplified”

Sonics In the News: 2014 in Review

The past year was a renaissance for Sonics in the public eye. With a high volume of company announcements, product launches, customer wins, and partner initiatives, the company generated a steady stream of positive news and points of view from both business and technology perspectives.

Continue reading “Sonics In the News: 2014 in Review”


Earlier this month I had the distinct pleasure of attending the EDA Consortium’s (EDAC) prestigious Phil Kaufman award dinner. This year’s winner is Lucio Lanza, managing director of Lanza techVentures, LLC. Lucio is an EDA industry legend. We used to bump into each other often in the Cadence hallways after both of our companies had been acquired by Cadence around 1989. I truly appreciated Lucio’s leadership style with the Artisan board of directors when I was Vice President of Corporate Ventures there. Lucio’s strategic insights and steady pressure to keep us focused on the critical items were a major factor in Artisan’s success.

Continue reading “IP Is EDA”

OCP: The Journey Continues

Accellera Systems Initiative has released the tutorial “OCP: The Journey Continues” from the 2014 Design and Verification Conference. Now available online, the five-part tutorial presents the past, present and future of the Open Core Protocol IP interface socket standard, which was transferred to Accellera in 2013. The tutorial provides a basic introduction and then discusses a variety of topics crucial to the use of OCP in SoC designs: verification IP support, TLM 2.0 SystemC support and IP-XACT support. Presenters include Herve Alexanian of Sonics, Steve McMaster of Synopsys, Prashant Karandikar of Texas Instruments and me.

Continue reading “OCP: The Journey Continues”

Is IC Design Methodology at the Breaking Point

On Semiconductor Engineering, Randy Smith discusses the mounting evidence that traditional “waterfall” methods used to develop complex ICs are reaching the breaking point and discusses Agile software development methods to see what can be applied.

Continue reading “Is IC Design Methodology at the Breaking Point”