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DVFS is Dead, Long Live Holistic DVFS

September 6, 2017 | Don Dingee
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DVFS is Dead, Long Live Holistic DVFS

An industry survey some three years ago indicated only about one-quarter of all chip designers were using dynamic voltage and frequency scaling (DVFS). It’s likely most of those people who said they were implementing DVFS are deeply dependent upon a mobile operating system. For instance, Android offers a range of CPU governor software modules to optimize frequency and voltage levels for application throughput. While DVFS is already enabled in most hardened CPU and GPU cores, clusters and/or subsystems, the majority of SoC designers not tied to Android opt for simpler techniques like clock and power gating. Is there an opportunity for a more holistic DVFS approach that more SoC designers would embrace? Continue reading “DVFS is Dead, Long Live Holistic DVFS”

Is Designing Your Chip Architecture Like Driving a Car with No Pedals?

For those of you that have been reading my blogs or watching my presentations for a while, you will know I like to use cars for analogies. They represent a system that everyone understands at a user level, they are composed of many subsystems, the details of which can get pretty complicated if you dig deep. So today, you will see how most chip architectures are designed like having a car without a gas pedal – and what you can do about it. Continue reading “Is Designing Your Chip Architecture Like Driving a Car with No Pedals?”

Taking Energy Back from Next-Generation MCU Designs

Microamp-per-megahertz thinking served the microcontroller (MCU) community well for decades. As the focus shifts to connectivity and always-on use cases, bigger cores and wireless IP blocks push energy use in the wrong direction. Next-generation MCUs can ill afford to spend more energy just to manage themselves. Any mandatory software to make an MCU run usually frustrates customers considering design-ins. How does the MCU ecosystem manage energy moving forward? Continue reading “Taking Energy Back from Next-Generation MCU Designs”

Best Practices for Power Management in SoCs Today

Interview with a Power Management Architect

Dynamic Power Management has become a ‘must-have’ in Systems-on-a-Chip (SoC) design today because of tightening power budgets and rising transistor counts. These increases mainly stem from evolving market requirements for more device functionality and richer feature sets being made available to meet changing market requirements. The semiconductor industry has responded with a plethora of different solutions to these issues.

Semico Research Corp. conducted an interview with Jawad Haj-Yihia, a Power Management Architect formerly of Intel Corp. in Israel. The following article represents key aspects of that interview delving into many of the issues that confront Power Management Architects in the industry today. Continue reading “Best Practices for Power Management in SoCs Today”

Are Incredible Engineering Feats Treated As Commonplace Today?

Recently I attended a presentation at the Machine Learning Developers Conference held at the Santa Clara Convention Center. The presentation, “Overcoming the Memory System Challenge in Dataflow Processing”, was given jointly by Darren Jones of Wave Computing and Drew Wingard of Sonics. The presentation was indeed fascinating as Jones first described how dataflow processors are ideal for deep learning, especially as compared to using existing CPU and GPU architectures. Jones then showed some performance numbers for machine learning training using the Wave Computing solution. And that is when I had to scratch my head. I did not hear any gasps. Everyone just accepted this phenomenal piece of engineering – just took it in stride. Continue reading “Are Incredible Engineering Feats Treated As Commonplace Today?”

Free Trial Explores EPU IP and Automation

Last summer at 53DAC in Austin, Sonics rolled out a seminar with a formative strategy for its Energy Processing Unit, or EPU. After that session, I summarized the idea in my SemiWiki blog:

“The premise of an EPU is that power savings using software, even in a dedicated microcontroller, is relatively slow, perhaps 50 to 500 times slower than what hardware-based power control can handle. Faster speeds mean narrower moments of idle time can be exploited to save energy, and distributed, autonomous, deadlock-free ICE-Grain controllers mean many more of those moments can be processed all over the system-on-chip (SoC) – leaving the CPU to do real work.” Continue reading “Free Trial Explores EPU IP and Automation”

Behold the Intrinsic Value of IP

Understanding the intrinsic value of Intellectual Property is like beauty, it is in the eye of the beholder.  The beholder of IP Value is ultimately the user/consumer of that IP – the buyers. Buyers tend to value IP based upon their ability to utilize that IP to create competitive advantage, and therefore higher value for their end product. The IP Value figure above was created to capture this concept. Continue reading “Behold the Intrinsic Value of IP”

Advancing Agile Hardware Design With Advanced Configurability

The concept of Agile design has been in practice for a long time.  Agile Software development is probably most universally practiced in part because a robust support ecosystem exists: from tool suppliers and consultants to the techniques new generations of software developers are taught in school.  If I narrow my focus to just the design phase of software development, I see it’s accepted as law that software design should be parameterized.  No matter what modern language you are using, you invoke a procedure by calling it and passing parameters to specify both data and control (options). With this design style, you can accept calls to use features that are specified, but not yet implemented. More importantly, it makes it easier to reuse the code in other designs or in other places in your design. Reuse is a key principle in applying Agile techniques in software design. Continue reading “Advancing Agile Hardware Design With Advanced Configurability”

The History of Power (Energy) Management in IC Design

Power management in IC design is loaded with exciting new developments. There have been attempts to solve power-related issues by altering the overall semiconductor process, biasing selected portions of a design, implementing various power distribution structures, introducing power gating, changing on chip network architectures, introducing microprocessor-based power channels, introducing energy processing units, and even more. Before jumping right into this topic, I think it’s best to provide an overview of what got us to this point.  In future posts, I’ll delve more into the state of the art and the important trends affecting the future of power-efficient IC design. Continue reading “The History of Power (Energy) Management in IC Design”

Everything is Here!

Doing business with Sonics has never been easier than in 2017. We just launched a re-designed web site that provides everything you need to know about our EPU and NoC technologies in a quick and easy to find format. Whether you are a power architect looking to save energy or an SoC designer searching for chip integration and interconnect solutions, we’ve crafted a thoughtful customer journey specifically for you. Our content-driven site takes you from understanding the problems associated with on-chip power management and chip integration through our products and solutions to serious consideration. Continue reading “Everything is Here!”