Power management in IC design is loaded with exciting new developments. There have been attempts to solve power-related issues by altering the overall semiconductor process, biasing selected portions of a design, implementing various power distribution structures, introducing power gating, changing on chip network architectures, introducing microprocessor-based power channels, introducing energy processing units, and even more. Before jumping right into this topic, I think it’s best to provide an overview of what got us to this point. In future posts, I’ll delve more into the state of the art and the important trends affecting the future of power-efficient IC design. “The History of Power (Energy) Management in IC Design”
Doing business with Sonics has never been easier than in 2017. We just launched a re-designed web site that provides everything you need to know about our EPU and NoC technologies in a quick and easy to find format. Whether you are a power architect looking to save energy or an SoC designer searching for chip integration and interconnect solutions, we’ve crafted a thoughtful customer journey specifically for you. Our content-driven site takes you from understanding the problems associated with on-chip power management and chip integration through our products and solutions to serious consideration. “Everything is Here!”
Why everyone needs to start taking power more seriously, and what you can do about it.
Energy is a finite resource, which means it’s not someone else’s problem. It’s everyone’s problem.
This isn’t just another doom and gloom prediction. Energy consumption has been rising steadily for decades. Unfortunately, it has been increasing at a faster rate than energy production. A Semiconductor Industry Association report entitled, “Rebooting the IT Revolution: A Call to Action,” says we could run out of energy to power computers by 2040.
Thanks for visiting us. After 20 years of business success serving the on-chip communication needs of system architects and SoC designers, Sonics has turned its attention to the issue of power management. We have expanded our technology and product portfolio to address the critical issue of saving on-chip power. Every design team and engineer developing chips faces this challenge today, from expert power architects making their chips more efficient to those attempting to optimize their power architecture for the very first time. “Welcome to our new website!”
Complexity and flexibility are the real drivers of fabric choice, not the number of initiators and targets. Since I first helped introduce the concept of applying networking techniques to address SoC integration challenges in 2007, I have been asked many hundreds of times how to determine when and where to best use an on-chip network (NoC) instead of a passive interconnect network (PIN)? Is there a minimum number of initiators and targets below which it makes more sense to use a PIN for the SoC architecture in “smaller” designs? “NoC Versus PIN: Size Matters”
Make vs. buy isn’t as simple a decision as it might appear. When companies consider purchasing Semiconductor IP (SIP), they often have a strict procedure for evaluating third-party vendors and their products. If they don’t have a set way of evaluating IP, the Global Semiconductor Alliance (GSA) has developed a Hard IP Licensing Risk Assessment Tool to aid in assessing the value of IP (there is also a quality assessment tool). This aid is part of the GSA IP ecosystem Tool Suite and is complementary to the entire industry – regardless of member status within GSA. It is a great tool suite and many companies have similar methodologies they use when considering the purchase of SIP. “Don’t Forget To Consider Productivity In Semiconductor IP Evaluations”
Why a methodology for developing software is now required in hardware. History repeats itself, but frequently not in the exactly the same place. The problems faced by system engineering teams today rising complexity, shorter market windows and more issues involving interactions that affect everything from dynamic power and leakage current to electromigration and finFET design mirror the kinds of top-down issues that software developers began encountering more than two decades ago. “Get Agile”
There are four primary failure modes associated with NoCs. Recently, the reliability features of on-chip network (NoC) IP have received much attention. One reason for this focus has been the rush of companies to get into the automotive electronics market and the explosion of new automotive features being implemented in electronic systems. While the details may vary, the high-level view of on-chip network reliability is really quite simple. “NoC Reliability: Simplified”
The past year was a renaissance for Sonics in the public eye. With a high volume of company announcements, product launches, customer wins, and partner initiatives, the company generated a steady stream of positive news and points of view from both business and technology perspectives.
Earlier this month I had the distinct pleasure of attending the EDA Consortium’s (EDAC) prestigious Phil Kaufman award dinner. This year’s winner is Lucio Lanza, managing director of Lanza techVentures, LLC. Lucio is an EDA industry legend. We used to bump into each other often in the Cadence hallways after both of our companies had been acquired by Cadence around 1989. I truly appreciated Lucio’s leadership style with the Artisan board of directors when I was Vice President of Corporate Ventures there. Lucio’s strategic insights and steady pressure to keep us focused on the critical items were a major factor in Artisan’s success.